A conventional VDMOS device includes a semi-conductor wafer in which source, body and drain regions of alternate conductivity type are disposed in series. A portion of the body region is adjacent to a first wafer surface and is bounded by the source and drain regions at that surface so as to define the length and width of a channel region in the body region. A gate electrode, separated from the first wafer surface by an oxide layer, overlies the channel region. A source electrode is disposed on the first surface so as to ohmically contact both the source and body regions, and a drain electrode is disposed on the second surface in ohmic contact with the drain region. The portion of the body region that is contacted by the source electrode is separated from the channel region, at the first surface, by the source region. To facilitate the connection between the source electrode and the body region, the body region typically incorporates a contact portion which is of the same conductivity type as the remainder of the body region but is of relatively high conductivity compared thereto.
During device operation, an appropriate voltage on the gate electrode inverts the conductivity type of the body region in that portion of the channel region that is contiguous with the wafer surface. The so-called inversion channel thereby produced permits a unipolar current flow between the source and drain regions. This unipolar electron flow (for an N channel device) or hole flow (for a P channel device) is selectively modulated by the voltage applied to the gate electrode. However, this source/body/drain structure inherently also produces a parasitic NPN or PNP bipolar transistor which is detrimental to the MOSFET performance.
In an effort to reduce the effects of this parasitic bipolar transistor a variety of structures have been suggested. For example, see U.S. patent application Ser. No. 582,601, VERTICAL MOSFET WITH REDUCED BIPOLAR EFFECTS AND METHOD FOR MAKING SAME, L. A. Goodman et al. filed Feb. 22, 1984; Ser. No. 605,427, MOSFET WITH REDUCED BIPOLAR EFFECTS, J. M. S. Neilson et al. filed Apr. 30, 1984; and U.S. Pat. No. 4,072,975, INSULATED GATE FIELD EFFECT TRANSISTOR, A. Ishitani, Feb. 7, 1978. In a further effort to effectively reduce the parasitic bipolar transistor, the configuration of the present invention was conceived. Furthermore, the structure of the present invention permits greater manufacturing tolerances and a commensurate improvement in manufacturing yield, so as to be advantageous even if the effects of the parasitic bipolar transistor were unaltered.